As the integration of semiconductor devices has increased, the line width and other critical dimensions of patterns in the devices have decreased. Thus, techniques for forming finer, more precise patterns are desirable. When the design rule for a semiconductor device is reduced, the line width of gate structures in the device may be reduced. Thus, metal oxide semiconductor (MOS) transistors having recessed gate electrodes have been provided to increase the length of the channel of such transistors.
FIGS. 1A and 1B are cross-sectional diagrams illustrating a conventional recess. FIG. 1A is taken along a first direction (the direction in which the active region extends). FIG. 1B is taken along a second direction that is substantially perpendicular to the first direction. A word line may run substantially parallel to the second direction.
As shown in FIG. 1B, if a recess 14 in a conventional semiconductor device is formed by partially etching an active region of a semiconductor substrate 10, a silicon fence 16 that extends in a first direction (the direction in which the active region extends) may be formed on a sidewall of an isolation layer 12. As shown in FIG. 1A, a wet etching process may be performed to remove the silicon fence 16 from the sidewall of the isolation layer 12 after the recess 14 is formed. The wet etch, however, may recess a sidewall of the recess 14 toward the isolation layer 14, thereby generating a bowing defect. In addition, a critical dimension (CD) of the recess 14 may increase in the wet etching process which can result in alignment errors in succeeding processes.